1. Field of the Invention
The present invention relates to a semiconductor circuit device comprising a receiver circuit, and more particularly to a higher-speed operation and a lower power consumption of the circuit.
2. Description of the Background Art
FIG. 4 shows a basic configuration of a semiconductor device in the prior art.
In FIG. 4, a driving circuit 3P for generating a transfer signal includes an inverter circuit 4P. An input terminal of the driving circuit 3P is connected to a signal line for transferring an output signal from an ante-stage circuit and an output terminal thereof is connected to one end of a transfer signal line 1P for transferring the transfer signal. Further, the other end of the transfer signal line 1P is connected to an input terminal of a receiver circuit 5P.
The receiver circuit 5P includes an inverter circuit 100 and an output terminal thereof is connected to an output signal line 6P for transferring an output signal from the receiver circuit 5P to a subsequent-stage circuit.
Furthermore, capacitances such as wiring parasitic capacitance applied to the transfer signal line 1P, which exist between a potential of the transfer signal line 1P and a ground potential, are represented by 2P conceptually as a single capacitance in FIG. 4.
Now, an operation of the prior-art semiconductor circuit device of FIG. 4 will be studied below.
With high integration of the semiconductor circuit device, in recent, times the number of circuits in the semiconductor circuit device dramatically increases, and at the same time the lengths of signal lines for connecting these circuits have increased. Thus, (i) when many circuits are connected to a signal line or (ii) when a signal line is very long, a value of the capacitance 2P of FIG. 4, which includes gate capacitance and diffusion capacitance of circuits and parasitic capacitance between the potential of the signal line and the ground potential, becomes very large. In this case, with an increase of the value of the capacitance 2P, a rise time for changing a potential of the transfer signal inputted to the receiver circuit 5P from the ground potential to the power-supply potential or a fall time for changing a potential of the transfer signal from the power-supply potential to the ground potential becomes very long.
In the prior-art receiver circuit 5P, however, the output signal from the inverter circuit 100 is not outputted until the potential of the transfer signal changes to at least half of the power-supply potential since the inverter circuit 100 consists of a P-type MOS transistor and an N-type MOS transistor which are ordinarily so designed as to have almost the same driving power. Therefore, a delay time of the output signal from the receiver circuit 5P becomes still larger due to still longer rise and fall times of the transfer signal inputted to the inverter circuit 100 with an increase of the value of the capacitance 2P.
Though it is necessary to suppress an increase of the rise or fall time in order to solve the above problems, it seems difficult to take radical measures in terms of configuration of the present semiconductor circuit device.
On the one hand, as one of solutions of these problems, it is conceivable to increase the driving power of the driving circuit 3P of FIG. 4, specifically, to increase the transistor size of the inverter circuit 4P. This solution allows a decrease of the delay time of the transfer signal, but arises a new problem of higher power consumption of the driving circuit 3P.
On the other hand, a technique for higher speed operation of the receiver circuit is proposed in Japanese Patent Application Laid Open Gazette 9-161484. In this prior art, a current mirror differential amplifier circuit serving only for the rise of the transfer signal and another current mirror differential amplifier circuit serving only for the fall of the transfer signal are separately provided and outputs of these circuits are selectively outputted.
The current mirror differential amplifier circuit serving only for the rise and that only for the fall proposed in the prior art, however, receive the transfer signal and a reference voltage signal as input signals, and the reference voltage signal is set to a constant level. For example, if the reference voltage signal is set to achieve a higher speed operation on the rise of the transfer signal, it is impossible to achieve a high-speed operation on the fall. Conversely, if the reference voltage signal is set to achieve a higher speed operation on the fall of the input signal, it interferes with a high-speed operation on the rise. Therefore, in this document, to ensure a sufficient operation speed on both the rise and fall of the transfer signal, a value of the reference voltage signal is set to a voltage value intermediate between the high-potential power supply and low-potential power supply. In short, the prior art performs substantially the same operation as the receiver circuit 5P of FIG. 4, and it has to be admitted that the prior art can not work as an effective solution of the above problem.
Further, it is impossible, in the circuits proposed in the prior art, to achieve a lower power consumption since also in a stationary state after the rise or fall of the transfer signal, a DC current flows in a path consisting of a MOS transistor receiving the reference signal, another MOS transistor which is a constituent of a current mirror and connected to the MOS transistor and still another MOS transistor serving as a constant-current power supply.
One of solutions of the above problem is proposed in Japanese Patent Application Laid Open Gazette 63-246925. The prior art reduces both the rise and fall delay times by setting different input threshold voltages for the rise time and the fall time of the transfer signal in a CMOS inverter, to achieve a higher speed operation of the inverter circuit.
With a detailed study on an operation of the inverter circuit in the prior art, however, it is found that a pass current flows across the high-potential power supply and the ground potential since a PMOS transistor whose gate electrode is connected to the transfer signal and source electrode is connected to the high-potential power supply is in an on state at some point near a level which exceeds the input threshold voltage of the circuit in a change of the transfer signal from "L" level to "H" level. The pass current blocks a change of an output signal to "L" level, and therefore a sufficiently high-speed operation, as compared with a conventional inverter circuit, is not achieved in the circuit of the prior art.